1. Field of the Invention
The invention lies in the fields of semiconductors and semiconductor manufacture. The present invention relates to a method for producing a semiconductor device and to a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits using MOS transistors has been increasing. With this realization of high integration, MOS transistors used in such integrated circuits have been miniaturized to the nano-scale. With the progress of such miniaturization of MOS transistors, there has been a problem in that it is difficult to suppress a leak current and the area occupied by circuits cannot be easily decreased from the standpoint of the requirement for ensuring a necessary amount of current. In order to solve this problem, a surrounding gate transistor (hereinafter referred to as “SGT”) has been proposed in which a source, a gate, and a drain are arranged in a perpendicular direction with respect to a substrate, and a gate electrode surrounds a pillar-shaped semiconductor layer (refer to, for example, Japanese unexamined patent application publications Nos. 2-71556, 2-188966, and 3-145761)
According to that technology, by using, as a gate electrode, a metal rather than a polysilicon, depletion can be suppressed and the resistance of the gate electrode can be lowered. However, in production steps after the formation of a metal gate, it is necessary to constantly consider metal contamination due to the metal gate.
In an existing method for producing an SGT, a silicon pillar on which a nitride film hard mask is formed in a pillar shape is formed, a diffusion layer is formed in a lower portion of the silicon pillar, a gate material is then deposited, the gate material is then planarized and etched back, and an insulating film sidewall is formed on the side wall of the silicon pillar and the nitride film hard mask. Subsequently, a resist pattern for forming a gate line is formed, the gate material is etched, the nitride film hard mask is then removed, and a diffusion layer is formed in an upper portion of the silicon pillar (refer to, for example, Japanese unexamined patent application publication No. 2009-182317).
In that method, a diffusion layer in a lower portion of a silicon pillar is formed, a gate electrode is then formed, and a diffusion layer is formed in an upper portion of the silicon pillar. Since the diffusion rate of boron is high and the diffusion rate of arsenic is low, when a so-called complementary metal oxide semiconductor (CMOS) SGT is formed, it is difficult to conduct optimum heat treatment on both a negative-channel metal oxide semiconductor (NMOS) and a positive-channel metal oxide semiconductor (PMOS). Accordingly, the diffusion layer in the lower portion of the silicon pillar and the diffusion layer in the upper portion thereof are separately formed and the nitride film hard mask is removed, and thus the number of steps is increased.
In another existing method for producing an SGT, a silicon pillar is formed, and a diffusion layer is then formed in each of an upper portion and a lower portion of the silicon pillar, and a gate material is deposited. Subsequently, the gate material is planarized and etched back, an insulating film sidewall is formed on the side wall of the silicon pillar. Subsequently, the gate material is etched to form a floating gate, and the insulating film sidewall is then removed (refer to, for example, Japanese unexamined patent application publication No. 2006-310651).
In that method, in the step of etching the gate material to form the floating gate, only a gate insulating film is provided on the upper portion of the silicon pillar. Consequently, the gate insulating film may be etched during the etching, and thus the silicon pillar may be etched. Furthermore, since the insulating film sidewall is removed after the formation of the floating gate, the number of steps is increased.